To integrate hardware approach in the error check of a processor with software approach.
Routers 14A and 14B are connected to subprocessor systems 10A and 10B as one duplex pair of a multiprocessor system, and I/O packet interfaces 16A and 16B are connected to the routers. A message packet is copied by the routers and sent by a method for surely synchronizing both the paired systems. Since the interruption issued from an I/O element is transmitted by the message packet while containing the information on the factor of interruption similarly to the other information transfer, the interruption can be protected by a CRC and it is not necessary to determine the factor from the side of a CPU. The message packet sent through an I/O has the information of originator or destination and while referring to an external source, for which access to a memory is permitted, from an access suitability verify and transform (AVT) table, a reception CPU verifies whether or not the access is to be permitted.
BUNTON WILIAM P
CUTTS JR RICHARD W
KLECKA JAMES S
KRAUSE JOHN C
WATSON WILLIAM J
ZALZALA LINDA E
