To improve analysis accuracy of failure analysis.

A detection example 3 using a circuit graph is shown in (D). The detection example 3 is a detection example which uses past failure occurrence rates. More specifically, a failure analysis method in the detection example 3 includes: dividing a chip in a mesh state and using a failure map recording the failure occurrence rate for each region; mapping portions that are laid out in a region R having the high failure occurrence rate of the failure map M in a circuit graph; and thereby detecting links Lx, La, Lb, and Lc in the region R as failure candidates among a group of links in a chain line back-traced from nodes Na and Nb.