Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
FAILURE ANALYSIS METHOD OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2003066117
Kind Code:
A
Abstract:

To detect a disconnection of lower-layer wiring without removing upper-layer wiring in a semiconductor device of a multilayer interconnection structure.

In the analysis of a disconnection in the lower-layer wiring 4 at the semiconductor device in a multilayer interconnection structure having the lower-layer wiring 4 and upper-layer wiring 6, electron beams are applied to the lower-layer wiring 4 by a high-acceleration voltage that penetrates the upper-layer wiring 6 when applying electron beams to the lower-layer wiring 4, thus detecting the disconnection in the lower-layer wiring 4 without removing the upper-layer wiring.


Inventors:
KANEKO MAMORU
Application Number:
JP2001258957A
Publication Date:
March 05, 2003
Filing Date:
August 29, 2001
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SANYO ELECTRIC CO
International Classes:
G01R31/02; G01R31/302; H01J37/28; H01L21/3205; H01L21/66; H01L23/52; G01R1/06; (IPC1-7): G01R31/302; G01R1/06; G01R31/02; H01J37/28; H01L21/3205; H01L21/66
Attorney, Agent or Firm:
Katsuhiko Sudo (1 outside)