Title:
FAILURE ANALYZER FOR SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2605607
Kind Code:
B2
Abstract:
PURPOSE: To provide an automated device performing failure analysis for semiconductor integrated circuit in a short time.
CONSTITUTION: Secondary electrons 15 of electron beam 9 cast on a semiconductor integrated circuit 8 is detected by a sensor 10 and by using electric potential distribution image, the failure analysis is performed. A test pattern is controlled by a gate generation circuit 11 and a computer 12, and a method to prolong the time for inputting the specified test pattern longer than the other ones is used, by automatically synchronizing it with the test pattern impressing, an electric potential image with small effect of charge-up is obtained with this device.
Inventors:
Yasuko Hanagama
Toyoichi Nakamura
Kiyoshi Futagawa
Toru Tsujide
Toyoichi Nakamura
Kiyoshi Futagawa
Toru Tsujide
Application Number:
JP30824593A
Publication Date:
April 30, 1997
Filing Date:
December 08, 1993
Export Citation:
Assignee:
NEC
International Classes:
G01R31/307; H01L21/66; G01R31/302; (IPC1-7): G01R31/302; H01L21/66
Domestic Patent References:
| JP631040A | ||||
| JP310177A | ||||
| JP3161948A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)