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Title:
FAILURE DETECTING CIRCUIT IN TIME DIVISION SWITCH
Document Type and Number:
Japanese Patent JPS5966256
Kind Code:
A
Abstract:

PURPOSE: To detect the generation of a failure in a time division switch, by providing a synchronizing channel monitoring means to an output side of digital information storage means of one frame's share.

CONSTITUTION: A multiplexer 101 converts successively in series parallel digital information on an input highway, and stores it in a speech bus memory 102. Suppose that a synchronizing pattern is inserted to the channel zero of each highway, the synchronizing signal passes through the memory 102 and is outputted to a coincidence detecting circuit 105. The relation between the output of the memory 102 and the value of a counter 109 is known from the content of a control memory 107 switching the address input of the memory 102. Thus, a failure detecting circuit 108 monitors the value of the counter 109 and when the synchronizing signal from the memory 102 and the correct synchronizing signal from a synchronizing signal generator 106 are not detected for coincidence 105, the circuit 108 discriminates it as the time division switch is failed.


Inventors:
AMADA EIICHI
SHIRASU HIROTOSHI
KUWABARA HIROSHI
SUZUKI TAHEI
MORITA TAKASHI
Application Number:
JP17614182A
Publication Date:
April 14, 1984
Filing Date:
October 08, 1982
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H04M3/22; H04M3/24; (IPC1-7): H04M3/22
Attorney, Agent or Firm:
Toshiyuki Usuda