Title:
FAILURE DIAGNOSER FOR LOGIC CIRCUIT GLITCH, FAILURE DIAGNOSING METHOD AND ITS PROGRAM
Document Type and Number:
Japanese Patent JP3908192
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To calculate the expectation of a logic circuit to tending to be a large scale and multi-layer wiring circuit at a function level for a short time, and estimate a failure point.
SOLUTION: The failure diagnoser estimates a failure point in a logic circuit, based on fail information taken from test results of a defective logic circuit, and is e.g. composed of an input unit 1, a fail extractor 1, a converter 3 for converting a logic circuit to a determination graph, a calculator 4 for calculating the expectation of the logic circuit, an estimator 5 for estimating a failure point in the logic circuit, a memory 6 for storing information, and an output unit 7.
Inventors:
Masato Nikaido
Application Number:
JP2003101815A
Publication Date:
April 25, 2007
Filing Date:
April 04, 2003
Export Citation:
Assignee:
NEC Electronics Corporation
International Classes:
G01R31/317; G01R31/28; (IPC1-7): G01R31/28
Domestic Patent References:
| JP2003194884A | ||||
| JP8212247A | ||||
| JP2689908B2 | ||||
| JP200167382A | ||||
| JP1062494A | ||||
| JP200046917A |
Attorney, Agent or Firm:
Tatsuo Tokumaru