Title:
FAILURE SENSING METHOD FOR INPUT CAPTURE CIRCUIT
Document Type and Number:
Japanese Patent JP3491372
Kind Code:
B2
Abstract:
PURPOSE: To establish a failure sensing method for input capture circuit, which can make failure sensing at a low cost without enlarging the magnitude of the circuit configuration.
CONSTITUTION: An input capture circuit is equipped with the first to fourth input capture register R1, R2, R3, R4 which latch the value on a timer T with a trigger input, and to the trigger input of the fourth capture register R4 of this circuit, the trigger inputs to be fed to the other capture registers R1, R2, R3 are fed via an OR circuit 1, and each time the first to third capture register R1, R2, R3 is triggered, the same timer value is latched in the fourth register 4. At failure sensing, the contents of the fourth register R4 are compared with the contents of the other R1, R2, R3 so as to know if they are identical, and thus the failure sensing can be performed at a low cost without enlarging the magnitude of the circuit configuration.
Inventors:
Katsuhiko Sano
Application Number:
JP6587395A
Publication Date:
January 26, 2004
Filing Date:
March 24, 1995
Export Citation:
Assignee:
Sumitomo Electric Industries, Ltd.
International Classes:
G04F10/04; B60T8/1761; B60T8/88; G01M17/007; G01R31/00; G06F11/18; H03K21/40; (IPC1-7): G06F11/18; B60T8/88; G01M17/007; G01R31/00; G04F10/04; H03K21/40
Domestic Patent References:
| JP715320A | ||||
| JP8156771A | ||||
| JP3107375U |
Attorney, Agent or Firm:
Bunji Kamata (2 outside)