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Patent Searching and Data


Title:
FAILURE SIMULATION DEVICE
Document Type and Number:
Japanese Patent JPH07121576
Kind Code:
A
Abstract:

PURPOSE: To obtain a failure simulation device capable of automatically extacting a signal line having the probability of generating a short-circuit failure and executing failure simulation for the extracted signal line.

CONSTITUTION: A wiring information extracting means 2 extracts wiring information from layout data 1. A short-circuit failure generating position specifying means 4 specifies a signal line whose short-circuit failure is to be detected based upon the extracted wiring information and a failure generation condition described in a failure generation condition file 3. A short-circuit simulation executing means 5 executes short-circuit failure simulation while supposing the generation of a shirt-circuit failure on the specified signal line. A short- circuit failure error information output means 6 outputs the simulation result as an error information list 7. Consequently a signal line to be failed can be specified by a uniform reference and the misinput of the signal line to be failed can be prevented. In addition, failure simulation execution time including preparation for the execution can be shortened.


Inventors:
HAMANO HIROYUKI
AKAMATSU YOSHIKAZU
Application Number:
JP26247893A
Publication Date:
May 12, 1995
Filing Date:
October 20, 1993
Export Citation:
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Assignee:
MITSUBISHI DENKI SEMICONDUCTOR
MITSUBISHI ELECTRIC CORP
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Attorney, Agent or Firm:
Takada Mamoru