Title:
FAST CMOS CURRENT SENSING AMPLIFIER
Document Type and Number:
Japanese Patent JPS61292293
Kind Code:
A
Abstract:
A CMOS current sense amplifier circuit for providing a high speed of operation includes a sense amplifier, a dummy sense amplifier and an operational sense amplifier. A memory array is formed of a plurality of core transistors which are arranged in a plurality of rows of word lines and a plurality of columns of bit-lines. A dummy bit-line is formed of a plurality of core transistors which are arranged in parallel along the rows of word lines. A first pass transistor and a plurality of Y-pass transistors are coupled between the sense amplifier and the memory array. Second and third pass transistors are coupled between the dummy sense amplifier and the dummy bit-line. A plurality of N-channel MOS transistors are used to clamp all of the bit-lines ih the array and dummy bit-line to a ground potential. The operational sense amplifier is responsive to the sense amplifier, dummy sense amplifier and the clamping transistors for generating an output signal which has a fast response time when making a low-to-high transition (that is when selecting an unprogrammed memory cell).
Inventors:
VENKATESH BHIMACHAR (US)
Application Number:
JP8398386A
Publication Date:
December 23, 1986
Filing Date:
April 10, 1986
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INC
International Classes:
G11C7/00; G11C11/419; G11C7/06; G11C7/14; G11C16/06; G11C17/00; (IPC1-7): G11C11/34
Domestic Patent References:
| JPS5968896A | 1984-04-18 | |||
| JPS59154692A | 1984-09-03 | |||
| JPS5812198A | 1983-01-24 | |||
| JPS5968897A | 1984-04-18 |
Attorney, Agent or Firm:
Kuro Fukami
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