Title:
フォールトトレラントシステム、フォールトトレラント方法及びプログラム
Document Type and Number:
Japanese Patent JP5664886
Kind Code:
B2
Abstract:
The present invention is a fault-tolerant system comprising: system failure logic means for editing system failure logic; and irrelevant component coverage means for identifying irrelevant components not having an effect on the system failure logic and isolating the irrelevant components based on the system failure logic provided by the system failure logic means.
Inventors:
向 剣文
Application Number:
JP2013547170A
Publication Date:
February 04, 2015
Filing Date:
November 27, 2012
Export Citation:
Assignee:
日本電気株式会社
International Classes:
G06F11/20; G06F11/22
Domestic Patent References:
| JPH05143570A | 1993-06-11 | |||
| JP2000235507A | 2000-08-29 | |||
| JP2008102562A | 2008-05-01 | |||
| JP2003345620A | 2003-12-05 | |||
| JP2010237855A | 2010-10-21 | |||
| JPH05143570A | 1993-06-11 | |||
| JP2000235507A | 2000-08-29 | |||
| JP2008102562A | 2008-05-01 | |||
| JP2003345620A | 2003-12-05 | |||
| JP2010237855A | 2010-10-21 |
Attorney, Agent or Firm:
Katsumi Uko