PURPOSE: To realize a fault detection/report mechanism with a small quantity of hardware by comparing the quantity of transmitted data with the quantity of stored data between two data processors which work asynchronously with each other.

CONSTITUTION: The data are transferred between an arithmetic circuit 1 and a memory circuit 2 which work with the clocks asynchronous with each other via a buffer 21. Under such conditions, an error detecting signal is transmitted from a comparator 6 when the value 102 held by a buffer counter 11 which counts the transfer value of the data 101 to the buffer 21 from the circuit 1 and the value 103 held by a counter 22 which counts the stored quantity of the data 101 received from the circuit 1 and registered in the buffer 21 exceed the value 106 held by a check designating register 5. Thus is it possible to realize a mechanism that performs the state control under the asynchronization with a small quantity of hardware.