Title:
FAULT DETECTION DEVICE
Document Type and Number:
Japanese Patent JP3184179
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a fault detection device capable of detecting a fault of a clocked buffer set in a multiplexer at the time of inspecting before the shipment without damaging a LSI chip or a rating device so that the input values of the multiplexer are reverse to each other.
SOLUTION: Because the values of A and B in a multiplexer 13 are in a reversal state, a fault is detect by a special test bench by outputting whether the value is from a clocked buffer of the multiplexer 13 or a clocked buffer to an arbitrary terminal of a LSI chip, therefore a fault of the clocked buffer set in the multiplexer 13 can be detected at the time of inspecting before the shipment.
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Inventors:
Teruichi Aki
Application Number:
JP11710999A
Publication Date:
July 09, 2001
Filing Date:
April 23, 1999
Export Citation:
Assignee:
NEC IC Microcomputer System Co., Ltd.
International Classes:
H03K19/00; G01R31/28; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Kihei Watanabe