Title:
FAULT DETECTION SYSTEM FOR ASYNCHRONOUS DATA TRANSFER DEVICE
Document Type and Number:
Japanese Patent JP3179367
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a circuit capable of informing a firmware of that the value of a time register cannot be ensured due to the occurrence of asynchronous error.
SOLUTION: An arithmetic processor is constituted of a transfer counter 24 for measuring the number of times of data transfer of a time register, busy flag 25 for indicating the transfer of the time register, interval counter 26 for monitoring a strobe interval, monitoring counter 27 for monitoring a strobe interval, monitoring counter 27 for monitoring the reception of an incorrect strobe after the end of transfer, and invalidity flag 30 for indicating that the time register is invalid. When asynchronous fault is detected through the interval counter 26 and the monitoring counter 27, the firmware is informed of that the value of the time register whose data transfer is being operated or ended cannot be ensured through the invalidity flag 30.
Inventors:
Masahiko Takato
Application Number:
JP12558497A
Publication Date:
June 25, 2001
Filing Date:
May 15, 1997
Export Citation:
Assignee:
Kofu NEC Corporation
International Classes:
G06F13/00; (IPC1-7): G06F13/00
Domestic Patent References:
| JP787047A | ||||
| JP6053875A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)