PURPOSE: To detect the trouble of every element processor by means of a barrier synchronous circuit and also to detect the bug of a program in a super-parallel computer system.

CONSTITUTION: This logical system includes the FF 14 to 54 which store the formation of barrier synchronization for the element processors 10 to 50, an FF 5 which is set when one of FF 14 to 54 becomes high, an AND gate 1 which transmits the high output when all of FF 14 to 54 become high, a time monitor mechanism 6 which starts the measurement of a fixed time after reception of the high output of the FF 5, outputs a high output signal and then switches the high output signal to the low one after a fixed time when the output of the gate 1 becomes high within a a fixed time, and the means (gates 11 to 51, FF 12 to 52, OR gate 2, FF 3) which detect and store the non-formation of barrier synchronization based on the output signal of the mechanism 6 and the outputs of FF 14 to 54. Then it is decided one of processors 10 to 50 has the abnormality when the output signal of the mechanism 6 is not switched to a low state from a high state after a fixed time.