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Patent Searching and Data


Title:
FAULT PROCESSING SYSTEM IN COMPOSITE LOOP CONSTITUTION LAN SYSTEM
Document Type and Number:
Japanese Patent JPH03175837
Kind Code:
A
Abstract:

PURPOSE: To previously prevent congestion in a gateway by abolishing frames with respect to nodes where faults occur before they enter the gateway when the fault occurs or at the time of congestion.

CONSTITUTION: The frames from the nodes on slave loops are branched in slave loop frame monitoring circuits 10 and are transferred to comparators 9. The comparators 9 compare communication data which are set in address holding memories 8. When they coincide, slave communication control circuits 11 abolish the frames from the slave loops. The frames from the nodes 2 on a master loop are branched in master loop frame monitoring circuits 5 through the master loop 3 and are transferred to comparators 6. The comparators 6 compare communication data which are set in the holding memories 8. When they coincide, master loop communication control circuits 7 abolish the frame from the master loop. The frames with respect to the nodes where the faults occurs, namely, the frames from the master loop and those from the slave loops are abolished before they enter the gateway.


Inventors:
SHIMIZU TOMOYOSHI
Application Number:
JP31424689A
Publication Date:
July 30, 1991
Filing Date:
December 05, 1989
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L12/42; (IPC1-7): H04L12/42
Attorney, Agent or Firm:
Masaki Yamakawa (3 outside)