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Title:
FAULT TEST DEVICE OF MICROPROCESSOR
Document Type and Number:
Japanese Patent JPH03177937
Kind Code:
A
Abstract:

PURPOSE: To easily test the stack fault of a bus by providing plural common input/output(CIO) bus driver which is connected between a microprocessor and the respective buses to be a test object.

CONSTITUTION: A counter 14 which is reset by a reset signal 12 inputted from a microprocessor is provided with four-bit outputs BO-B3, a bus test data selecting signal 34 is generated by supplying the AND 16 outputs 18 of output bits BO-B3 and a select gate 38 gives a test data signal 40 to a CIO bus driver 32. The bus signal is detected by responding to the given test data signal 40, a CIO input 46 is supplied to an all-zero detection OR gate 48 and an all-one detection AND gate 50 and an error signal 62 is generated by responding to the detected bus signal which indicates a bus fault. Thus, error detection with high reliability is efficiently executed.


Inventors:
SUKOTSUTO DAGURASU KURAAKU
KENISU KURUUDO HINTSU
JIYATSUKU KURISU RANDORUFU
MAAKU ROOREN RUUDOKUISUTO
TOOMASU MIRUTON UOOKAA
Application Number:
JP29998290A
Publication Date:
August 01, 1991
Filing Date:
November 07, 1990
Export Citation:
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Assignee:
IBM
International Classes:
G06F11/22; G06F11/267; G06F13/00; G06F15/78; (IPC1-7): G06F11/22; G06F13/00
Domestic Patent References:
JPH01135559U1989-09-18
Attorney, Agent or Firm:
Kiyoshi Goda (5 outside)