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Title:
FAULT TOLERANT COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JPH0916536
Kind Code:
A
Abstract:

To simplify a preceding graph as a non-determinative event record format to be used for a 'Manetho' fault tolerant system.

In the fault tolerant computer system provided with plural processors and plural recovery units A to C for operating plural processes, each of the units A to C is provided with a Jogging means for recording one action process to be operated in each processor, a message sent from an action process in its own recovery unit, and the sequence of non-determinative event information of all action processes, a history state means for maintaining the up-to-date state information of an action process in its own recovery unit, and a recovery means for starting a substitutive process by using the state information of the history state means in its own recovery unit. Consequently a preceding vector for recording the non-determinative event sequence of respective action processes is substituted for a preceding graph in a Manetho system using conventional technology.


Inventors:
POORU HARII
Application Number:
JP32864595A
Publication Date:
January 17, 1997
Filing Date:
December 18, 1995
Export Citation:
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Assignee:
HEWLETT PACKARD CO
International Classes:
G06F11/20; G06F11/14; G06F15/16; G06F15/167; G06F15/177; (IPC1-7): G06F15/16; G06F11/20
Attorney, Agent or Firm:
Tsukio Okada



 
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