PURPOSE: To suppress an error generating rate generated in the process of coding or decoding in an excellent way and to improve the conversion efficiency by providing a code conversion circuit and a latch circuit or the like and preventing a code error from being affected onto an adjacent channel bit.

CONSTITUTION: A video data symbolized in the unit of 8-bit is latched by a latch circuit 2 at first as an 8-bit parallel data, divided into high-order and low-order 4-bit via buffer circuits 3, 4 and outputted to a latch circuit 5 alternately. Then a 4-bit data latched in the circuit 5 is converted into an 8-bit channel bit at a code conversion circuit 6 and outputted while being subject to NRZI coding by a parallel serial conversion circuit 8 and an NRZ/NRZI coding circuit 9. In this case, 16 kinds of data bits from 0000 to 1111 are code-converted without excess/deficiency into any channel bit of channel bits 01000000-00000100 and a code 101 produced at the connection of the channel bits are bit-inverted into 010 as exception. Thus, the conversion efficiency is improved.