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Title:
FERROELECTRIC MEMORY AND ITS DRIVING METHOD
Document Type and Number:
Japanese Patent JP3662163
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To solve such a problem that it is required for a dummy cell to gener ate a reference potential for every read-out of each data cell connected to the same cell array, deterioration of dummy cells of which the number of times of read-out is more than that of data cells is aggravated, and an intermediate potential cannot be generated correctly.
SOLUTION: This device has ferroelectric capacitors, a memory cell array provided with at least three memory cells consisting of a first transistor and a second transistor connected in parallel to an electrode of one side of the ferroelectric capacitor, a first bit line to which each ferroelectric capacitor of the memory cell is connected in parallel through first transistor, a second bit line to which respective ferroelectric capacitors of plural memory circuits is connected through the second bit line, and a means judging logic '1' or logic '2' by comparing a potential of the first bit line with a potential of the second bit line.


Inventors:
Yasunari Hosoi
Application Number:
JP2000059881A
Publication Date:
June 22, 2005
Filing Date:
March 06, 2000
Export Citation:
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Assignee:
Sharp Corporation
International Classes:
G11C14/00; G11C11/22; H01L21/8242; H01L27/10; H01L27/108; H01L27/115; (IPC1-7): G11C11/22; H01L21/8242; H01L27/10; H01L27/108
Domestic Patent References:
JP11185481A
JP11261017A
JP7192476A
JP7093978A
JP2301093A
JP5114741A
JP10070248A
JP5013771A
JP5089692A
JP9097496A
Attorney, Agent or Firm:
Hiroshi Yamazaki
Atsushi Maeda
Yukinori Nakakura
Takaya Koike
Masaharu Kinoshita