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Title:
FERROELECTRIC MEMORY SENSING METHOD IN WHICH READ VOLTAGE IS DIFFERENT FROM WRITE VOLTAGE
Document Type and Number:
Japanese Patent JP3200009
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To enhance the data holding performance of a ferroelectric memory by using a pulse having a lower voltage than a usual voltage during writing operation to the ferroelectric memory and a pulse having a higher voltage than the usual voltage during writing operation.
SOLUTION: At first, signals of a word line WL, a plate line PL and a bit line Bit are in a logic 0. Further, a charge pump voltage, for instance, is approximately 4V and lower than the power supply of 5V. Next, a PL signal is energized by using a pulse of 4V and however, an electric charge is discharged again on a bit and a reverse bit lines. Next, the voltage waveform of a charge pump is stepped up to the level of 6V to boost a logic level voltage on the bit line to 6V and 0 and also boost a WL signal to 6V. Next, the PL signal is again made into the pulse of a logic 1, and the capacitors 16, 18 of a memory cell are saturated, thereby writing a desired data state into a ferroelectric memory cell 10.


Inventors:
Ruesch, Rodney A.
Golabi, Manooch
Application Number:
JP1996000076594
Publication Date:
June 15, 2001
Filing Date:
March 29, 1996
Export Citation:
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Assignee:
RAMTRON INTERNATL CORP
International Classes:
G11C14/00; G11C11/22; (IPC1-7): G11C11/22
Attorney, Agent or Firm:
社本 一夫 (外5名)



 
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