Title:
FERROELECTRIC MEMORY
Document Type and Number:
Japanese Patent JP3717097
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To batch-erase contents of a plurality of memory cells.
SOLUTION: The ferroelectric memory comprises a capacitor 13 connected between one end of a ferroelectric capacitor 11 and a common line COM0 of one row of each ferroelectric memory cell 10B, an erasing switch element 41 to be turned ON in response to activation of an erasing signal ERS and connected between the line COM and an erasing power source voltage VE, and an erasing switch element 42 to be turned ON in response to activation of the signal ERS and connected between a plate line PL0 and a conductor of a ground potential. An intermediate electrode is connected to a common line thereby omitting the capacitor 13.
Inventors:
Fukuda Motoyasu
Application Number:
JP21452298A
Publication Date:
November 16, 2005
Filing Date:
July 29, 1998
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C14/00; G11C11/22; (IPC1-7): G11C11/22
Domestic Patent References:
| JP6259957A |
Attorney, Agent or Firm:
Shinkichi Matsumoto