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Title:
FET DRIVING CIRCUIT
Document Type and Number:
Japanese Patent JPH06188703
Kind Code:
A
Abstract:

PURPOSE: To reduce the power consumption, and to reduce the size of the device and enable high-speed switching by equipping the FET driving circuit with a switched capacitor and discharging electric charges accumulated in the input capacitance of an FET.

CONSTITUTION: When a transistor(TR) Q4 of a control part 30 turns on, the FET Q1 is applied with a sufficient gate voltage VGS to turn on. TRs Q2 and Q3, on the other hand, are reversely biased to turn off and electric charges are accumulated in a capacitor C1 through a diode D1, the capacitor C1, and a diode C2. When a TR Q4 of the control part 30 turns off, a base current i3 is generated at a resistance R1, the C1, the TR Q2, and a resistance R3 with the electric charges accumulated in the C1 and the TRs Q2 and Q3 turn on. Consequently, the electric charges accumulated in the input capacitance of the FET Q1 can speedily be discharged.


Inventors:
YOSHIDA HIROAKI
Application Number:
JP35413192A
Publication Date:
July 08, 1994
Filing Date:
December 15, 1992
Export Citation:
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Assignee:
SONY CORP
International Classes:
H02M3/28; H03K17/04; H03K17/687; (IPC1-7): H03K17/04; H02M3/28; H03K17/687
Attorney, Agent or Firm:
Oka-saki-Shintaro (1 person outside)



 
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