PURPOSE: To reduce the load of a memory bus set between a cache and a main memory and to increase the processing speed by securing a constitution where a CPU informs the cache of a branch decision control signal to have a mishit with execution of a branch instruction and suppressing the supply of the mishit given from the main memory when the branching conditions are not decided yet.
CONSTITUTION: When a branch instruction is carried out, a CPU 1 informs a cache 2 of a fetch address. In a hit mode, the branch instruction and the data are sent to the CPU 1. In a mishit mode, the branch is decided when a branch decision control signal 7 is turned off. Then the instruction and the data are written in a cache 2 from a main memory 3 and at the same time these instruction and data are sent to the CPU 1. On the other hand, the brach is not decided yet when the signal 7 is turned on. Then a process where the instructions and the data are written in the cache 2 from the memory 3 is suppressed.
NODA TAKAHITO
KAMISAKA YUJI
NONOMURA KAZUYASU
WATABE TORU
TAKENO TAKUMI
KATO SHINYA
POONSHIYAI CHIYONSUWANNAPAISAA
