Title:
FFT DEVICE AND HIGHER HARMONIC DETECTING DEVICE FOR ELECTRIC POWER
Document Type and Number:
Japanese Patent JP3864488
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a specific number of arithmetic results from a final arithmetic stage by equipping each arithmetic stage with a delay element and pipelining them, and then performing butterfly operation by each arithmetic stage each time one sampling value is inputted.
SOLUTION: The number of samples is set to 2N and the order of 1st to 5th arithmetic stages is set to (n); and N arithmetic stages consisting of delay elements 12, 22, 32, 42, and 52 which hold 2n-1 signal values sent from precedent stages 2N-n times and output them and butterfly arithmetic parts 13, 23, 33, and 43 which combine the 2n-1 signal values outputted from the delay elements 12, 22, 32, 42, and 52 with 2n-1 signal values sent from the precedent stages and perform butterfly operations are pipelined in order. Consequently, the 1st to 5th arithmetic stages can obtain 2N arithmetic results in real time at all times each time one sampling value is inputted.
Inventors:
Shinya Kawada
Toru Katsuno
Toru Katsuno
Application Number:
JP9539797A
Publication Date:
December 27, 2006
Filing Date:
April 14, 1997
Export Citation:
Assignee:
Fuji Electric Systems Co., Ltd.
International Classes:
G01R23/16; G06F17/14; G01R23/20; G01R25/00; (IPC1-7): G06F17/14; G01R23/16; G01R23/20; G01R25/00
Domestic Patent References:
JP59055573A | ||||
JP6044300B2 | ||||
JP3246763A | ||||
JP10282162A |
Attorney, Agent or Firm:
Hiroshi Yamamoto
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