To provide a hetero-junction FET which is equipped with a barrier layer that is low in series resistance to a source and a drain electrode while possessing a high barrier function to a gate electrode.

A buffer layer 43, a non-doped InGaAs channel layer 44, a barrier layer 45 composed of a plurality of layers, and an n+-type contact layer 46 of thickness 50 nm are formed on a semi-insulating GaAs substrate 42. The multilayered barrier layer 45 has a three-layered structure composed of an n-type AlGaAs layer 45a, a non-doped AlGaAs layer 45b of thickness 2.5 to 5 nm, and an n-type AlGaAs layer 54c of thickness 10 nm. A gate electrode 50 is formed on the n-type AlGaAs layer 54c in a recess 47 where the contact layer 46 is partially removed, and the bottom of the gate electrode 50 is brought into Schottky contact with the non-doped AlGaAs layer 45b as buried in the n-type AlGaAs layer 45c.