FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF

Title:

FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF

Document Type and Number:

Japanese Patent JP2763025

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To provide a field-effect transistor improved so as to prevent the deterioration of the high frequency characteristic and drain lag by reducing the parasitic capacitance between a shield layer and drain region.
SOLUTION: The most of a p-type shield layer 2 for shielding a substrate trap is formed below and apart from a channel region 3 and source region 6 and faces with a small area at a drain region 5 asymmetrically. It is formed by setting the end of a resist 12 on a gate electrode 4 and implanting ions as deep as reaching the shield layer 2 to self-matchedly change it and part of the shield layer 2 into an nN type region, the drain region 5. The ion implantation is made so shallow into the source as the shield layer 2 at the source region remains unchanged.

Inventors:

NOMAI MASANOBU

Application Number:

JP9262996A

Publication Date:

June 11, 1998

Filing Date:

April 15, 1996

Export Citation:

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Assignee:

NIPPON DENKI KK

International Classes:

H01L29/812; H01L21/338; (IPC1-7): H01L21/338; H01L29/812

Domestic Patent References:

JP9153498A

Attorney, Agent or Firm:

Yosuke Goto (2 outside)

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