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Title:
FIELD-EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPH01179460
Kind Code:
A
Abstract:

PURPOSE: To realize a high-output and high-yield superhigh-frequency InPFET by a method wherein a recess is provided in an N-type channel InP operating layer and a gate electrode for controlling a channel is provided on an undoped AlGaAs epitaxial crystal layer formed on the recess part.

CONSTITUTION: An N-type channel InP operating layer 2 of an impurity concentration of 1×1017cm-3 is grown on a semiinsulative InP substrate 1 in a thickness of 0.2μm by a vapor phase epitaxy method, for example. Then, a recess of a proper form is formed in the layer 2 by a normal etching method. Then, an undoped AlGaAs epitaxial layer 3 is grown in a thickness of 1000 by a molecular beam epitaxy method, for example. Then, the layer 3 at ohmic contact parts is etched away. Lastly, a gate electrode 4 and source and drain electrodes 5 and 6 are formed by a normal method to realize a FET. According to this way, as an electric field concentration between the gate and the drain is relaxed at the time of application of a high drain voltage, an avalanche breakdown due to the electric field concentration stops hardly occurring.


Inventors:
MANO KAZUNORI
Application Number:
JP233188A
Publication Date:
July 17, 1989
Filing Date:
January 07, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
C01G15/00; H01L21/338; H01L29/205; H01L29/43; H01L29/80; H01L29/812; (IPC1-7): C01G15/00; H01L29/205; H01L29/80
Attorney, Agent or Firm:
Uchihara Shin



 
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