PURPOSE: To set a data delay time that is longer than an external signal period by controlling the transfer timing and the initial set timing of a write-in address by an external signal, and making the reset of a write address generating means and a read-out address generating means to be an internal reset.

CONSTITUTION: Write start addresses are successively transferred on cascade connected latch circuits 41, 42 at the timing of a write load signal WLOAD, the write start address is selected by selecting one of the latch data of the latch circuits 41, 42 based on the data delay time, and this selected output is set to a read address counter 38 as an initial value at the timing of a read load signal RLOAD. Then, the transfer timing and the load timing of the write start address are controlled by the external signal, and the reset control of the write address counter 36 is executed by the internal reset. Thus, the data delay time that is longer than the external signal period can be set.