PURPOSE: To detect both the same data errors by comparing the readout data of a second FIFO inputted to delay the inputted data of a first FIFO by A quantity and the data delayed the readout data of the first FIFO by the same A quantity, detecting the data error and resetting.

CONSTITUTION: The input data (a) of the FIFO circuit 3 is delayed by one bit with a delayed circuit 4 and inputted to the FIFO circuit 5, the readout data (e) is attained to the output of the circuit 5. Further, the readout data (d) of the circuit 3 is delayed by the same delayed quantity as the circuit 5 with the delayed circuit 6, a delayed data (g) is attained. The data (g), (e) are compared by a comparator circuit 7, a resetting signal (h) is outputted to the circuits 3, 5 and a counter 8, when the output data are mistaken simultaneously in the circuits 3, 5 by an AND circuit 10, the signal (h) is outputted. Thus, the data error when the both readout data are mistaken similarly is detected.