Title:
FILL-IN SIGNAL UNIT PROCESSING CIRCUIT FOR MULTIPLE PROCESSING
Document Type and Number:
Japanese Patent JP3353704
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a fill-in signal unit processing circuit for multiple processing capable of reducing the load of a firmware processing without degrading link quality by discriminating a fill-in signal unit required for a response processing from a received signal unit and eliminating the fill-in signal unit for time fill.
SOLUTION: The fill-in signal unit to be transmitted for the time fill is deleted at a level 2 in No.7 signal system, only fill-in signal unit required for the response processing is detected and the processing of the level 2 is performed by the fill-in signal unit processing circuit 6 for multiple processing. Namely, the occurrence of congestion is reduced since the processing of the fill-in signal unit depends on processing ability most and the processing is performed by extracting only the fill-in signal unit required for the response processing.
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Inventors:
Mikiko Miyagishi
Application Number:
JP13982398A
Publication Date:
December 03, 2002
Filing Date:
May 21, 1998
Export Citation:
Assignee:
NEC
International Classes:
H04M7/06; (IPC1-7): H04M7/06
Domestic Patent References:
| JP639338A | ||||
| JP321153A | ||||
| JP6161554A | ||||
| JP2135965A | ||||
| JP251934A |
Attorney, Agent or Firm:
Hiroo Suzuki