Title:
フィルタ演算処理装置、フィルタ演算方法、及び効果付与装置
Document Type and Number:
Japanese Patent JP6724828
Kind Code:
B2
Abstract:
A signal processing apparatus has a first memory in which plural pieces of FIR coefficient data used for implementing an FIR filter algorithm are stored, a second memory which stores plural pieces of input data to be subjected to the FIR filter algorithm, and a processor implements the FIR filter algorithm using the plural pieces of FIR coefficient data stored in the first memory and the plural pieces of input data stored in the second memory as many times as the number corresponding to a designated filter order, in which filter algorithm each piece of coefficient data and each piece of input data are multiplied together and resultant products are summed up. The signal processing apparatus is provided, which can implement plural sorts of FIR filter algorithms of filter order which can be changed flexibly.
Inventors:
Yokota Masuo
Application Number:
JP2017049459A
Publication Date:
July 15, 2020
Filing Date:
March 15, 2017
Export Citation:
Assignee:
CASIO COMPUTER CO.,LTD.
International Classes:
G10H1/00; G10K15/04; H03H17/06; H03H17/08
Domestic Patent References:
| JP60177713A | ||||
| JP9185373A | ||||
| JP2008197284A | ||||
| JP64068799A | ||||
| JP2000267682A |
Foreign References:
| US5814750 |
Other References:
山口 晶大,体験版シミュレータや評価キットで楽しみながら学ぶ これならわかる!DSP入門,トランジスタ技術,日本,CQ出版株式会社,2002年10月 1日,第39巻, 第10号,第147-186ページ
WILLIAM G. GARDNER,Efficient Convolution without Input-Output Delay,J. Audio Eng. Soc., Vol.43, No.3,1995年
WILLIAM G. GARDNER,Efficient Convolution without Input-Output Delay,J. Audio Eng. Soc., Vol.43, No.3,1995年
Attorney, Agent or Firm:
Yoshiyuki Osuga
Hiroyoshi Aoki
Amada Masayuki
Hiroyoshi Aoki
Amada Masayuki