Title:
FINE CONNECTION STRUCTURE
Document Type and Number:
Japanese Patent JPS63168028
Kind Code:
A
Abstract:
PURPOSE: To assure the electrical connection with high reliability at low temperature by a method wherein protruding electrodes on a semiconductor chip and Al electrodes on a substrate are connected through the intermediary of specific junction layers.
CONSTITUTION: In-Sn junction layers 4 are formed on protruding electrodes 3 on a semiconductor chip 1 while the electrodes 3 on chip 1 are connected to Al electrodes 6 on a mounting substrate 5 through the intermediary of the layers 4. Through these procedures, the layers 4 with low melting point and alloy junction property together with In-Sn alloy relatively soft and resistant to thermal fatigue can assure the electrical connection with high reliability at low temperature.
Inventors:
HORIO YASUHIKO
BESSHO YOSHIHIRO
BESSHO YOSHIHIRO
Application Number:
JP31104986A
Publication Date:
July 12, 1988
Filing Date:
December 29, 1986
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01C1/14; H01G4/228; H01L21/60; H05K3/34; (IPC1-7): H01C1/14; H01G1/14; H01L21/60; H05K3/34
Attorney, Agent or Firm:
Toshio Nakao