PURPOSE: To attain efficient data communication through the operation of a first-in first-out(FIFO) buffer circuit.

CONSTITUTION: Three data counter sections 8, 9, 31 are provided in an FIFO buffer circuit 30, and a 1st count-down counter section 8 is used to count number of words of a memory section 4 in the FIFO buffer circuit, to detect packet data in one unit from a write side control section 2 and to inform a 2nd count- down counter section 31 of the detected data. An up-down counter section 9 is used to detect packet data in one unit from a read side control section 3 and to inform a 2nd count-down counter section 31 of the detected data, and the 2nd count-down counter section 31 receives a notice of the end of count by the 1st count-down counter section 8 and informs the output side of the number of read waiting packet data in the FIFO buffer detected by the up-down counter section 9 after receiving the notice of the end of count by the 1st count- down counter section 8.