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Title:
FIRST-IN FIRST-OUT MEMORY
Document Type and Number:
Japanese Patent JPH0298728
Kind Code:
A
Abstract:

PURPOSE: To substantially shorten a fall-through time without the need to decrease storage capacity by providing an input control means for input from respective arrays which is coupled with respective input means and use a 1st logical function and an output control means for output from the respective arrays which is coupled with respective output means and uses a 2nd logical function.

CONSTITUTION: The FIFO(first-in first-out) memory 100 includes (k) ripple- through FIFO memory arrays 1011-1011, which each have (n) rows and (m) bits. Input to the respective FIFO memory array 101 is controlled by the input control means 102 and output is controlled by the output control means 103. Then one of the arrays is selected by the input control means 102 in each input operation in order so as to store input data in predetermined order, and the output control means 103 selects the output from one of the arrays in the predetermined order in each output operation. Consequently, the FIFO memory is obtained which has a substantially shortened fall-through time.


Inventors:
YAN CHII WAN
POORU SUKOTSUTO
Application Number:
JP20112889A
Publication Date:
April 11, 1990
Filing Date:
August 01, 1989
Export Citation:
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Assignee:
ADVANCED MICRO DEVICES INC
International Classes:
G06F5/06; G06F5/16; G11C7/00; H03M9/00; (IPC1-7): G06F5/06; G11C7/00
Domestic Patent References:
JPS63168720A1988-07-12
JPS61127031A1986-06-14
JPS61112270A1986-05-30
JPS6111998A1986-01-20
Attorney, Agent or Firm:
Fukami Hisaro (2 outside)