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Title:
Non-volatile latch circuit
Document Type and Number:
Japanese Patent JP6288643
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce an area occupied by a non-volatile latch circuit using a resistance change storage element.SOLUTION: A non-volatile latch circuit 100 comprises: a memory cell 10 storing data in MTJ elements 11, 13; a shared writing control transistor 20 commonly connected to one ends of the MTJ elements 11, 13 of the plurality of memory cells 10; and a shared reading control transistor 30 commonly connected to one ends of the MTJ elements 11, 13 of the plurality of memory cells 10. The shared writing control transistor 20 causes writing current to flow through the MTJ elements 11, 13 by being turned on in response to a writing control signal. The shared reading control transistor 30 causes reading current to flow through the MTJ elements 11, 13 by being turned on in response to a reading control signal. The shared writing control transistor 20 and the shared reading control transistor 30 are turned on complementarily.

Inventors:
Takahiro Hanyu
Daisuke Suzuki
Hideo Ohno
Tetsuro Endo
Masanori Natsui
Akira Mochizuki
Keizo Kinoshita
Shoji Ikeda
Hideo Sato
Fukami Shunsuke
Application Number:
JP2014058889A
Publication Date:
March 07, 2018
Filing Date:
March 20, 2014
Export Citation:
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Assignee:
Tohoku University
International Classes:
G11C11/16
Domestic Patent References:
JP2012169011A
JP2010067332A
JP2013131271A
JP2004220759A
Attorney, Agent or Firm:
Kimura Mitsuru
Hiroyoshi Sato
Takanori Mamoru