PURPOSE: To prevent the production of an erroneous flag by applying a hazard to shift registers of n-stage and using an AND means so as to AND an output of a pre-stage and an output of a final stage.

CONSTITUTION: A circuit generating a flag when a signal having a period being a multiple of m (m>2) of a clock period is inputted is provided with an n-stage shift resister 4 shifting the input signal by a multiple of n (n≥m) of the clock period and an AND means 5 ANDing a final stage output of the shift register 4 and an output of an optional stage within from the (n-2)th stage till the [n-(m-1)]th stage. Thus, when a hazard is inputted, it is converted into a pulse with the same period as the clock period at the 1st stage of the shift register 4, the resulting pulse is shifted sequentially by each clock period and an L level AND output is obtained by ANDing the n-stage output and the output from the preceding stage from the (n-2)th stage because of the production of a period over one clock period between the final stage output and the output of the preceding stage before the (n-2)th stage. Thus, the production of an erroneous flag is prevented.