Title:
FLAG SYNCHRONIZATION TYPE SERIAL DATA RECEIVER
Document Type and Number:
Japanese Patent JP3845024
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a flag synchronization type serial receiver in which the usage rate of a CPU in serial reception processing during serial data reception, and thus the implementation efficiency of another processing to be performed by the CPU is increased.
SOLUTION: A DMAC 28 is added, and data transfer is switched so as to be performed by the DMAC 28 instead of a CPU 26 after detection of a synchronization flag among processing to be started on a CPU 26 according to an interrupting signal from an SIO 20. Thus, a CPU 24 can be prevented from intervening the transfer of data after the detection of the synchronization flag, so that the load of the CPU 24 can be reduced, and that the implementation efficiency of another processing to be performed by the CPU 24 can be improved.
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Inventors:
Mitsuhiro Iida
Application Number:
JP2002021919A
Publication Date:
November 15, 2006
Filing Date:
January 30, 2002
Export Citation:
Assignee:
ADC Technology Co., Ltd.
International Classes:
G06F13/24; H04L29/02; G06F13/28; G06F13/38; (IPC1-7): H04L29/02; G06F13/24; G06F13/28; G06F13/38
Domestic Patent References:
| JP2001028581A | ||||
| JP2000299667A | ||||
| JP7244633A | ||||
| JP10262095A | ||||
| JP11289357A | ||||
| JP2001147875A |
Attorney, Agent or Firm:
Tsutomu Adachi
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