Title:
リダンダンシ選択回路を備えたフラッシュメモリ装置及びテスト方法
Document Type and Number:
Japanese Patent JP4439683
Kind Code:
B2
Abstract:
A semiconductor memory device includes a redundancy selection circuit. The redundancy selection circuit includes generating means for simultaneously generating a first redundancy address and a second redundancy address in response to the column address at a read cycle. The first redundancy address indicates whether the column address is defective, and the second redundancy address indicates the place where a defective one of the first selected columns is positioned. The redundancy selection circuit further includes means for generating redundancy selection signals each corresponding to the first selected columns in response to the first and second redundancy addresses. According to the present invention, the redundancy selection circuit stores defective addresses by use of flash EEPROM cells similar to those of the main memory cell. Addresses can be programmed, without limitation in the redundancy selection circuit. All the redundant memory cells of an array are tested.
Inventors:
Lee Bin
Application Number:
JP2000163367A
Publication Date:
March 24, 2010
Filing Date:
May 31, 2000
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO.,LTD.
International Classes:
G01R31/28; G06F12/16; G11C29/04; G11C16/06; G11C16/08; G11C17/00
Domestic Patent References:
| JP7153294A | ||||
| JP1109599A | ||||
| JP10097800A | ||||
| JP10172294A | ||||
| JP5074184A |
Attorney, Agent or Firm:
Makoto Hagiwara