Title:
フラッシュメモリおよびそれに関連する方法
Document Type and Number:
Japanese Patent JP5081923
Kind Code:
B2
Abstract:
In a method of operation, a flash memory cell is programmed, a word-line voltage is coupled to the flash memory cell, and a state of the flash memory cell is sensed at intervals to generate data to indicate a state of the flash memory cell. In a method of operation, a latch in a cache memory of a NAND flash memory is switched off, and the latch is initialized while the latch is switched off. A read voltage is coupled to a gate of a selected flash memory cell in the NAND flash memory where the selected flash memory cell is coupled to a bit-line, and the bit-line is coupled to an input of the latch while a voltage on the bit-line is changing.
Inventors:
Elmhurst, Daniel
Sanchin, Giovanni
Incarnachi, Michelle
Moschiano, Biollante
Diorio, Ercol
Sanchin, Giovanni
Incarnachi, Michelle
Moschiano, Biollante
Diorio, Ercol
Application Number:
JP2009544240A
Publication Date:
November 28, 2012
Filing Date:
December 21, 2007
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G11C16/02; G11C16/06
Domestic Patent References:
| JP2005196871A | ||||
| JP2006172523A | ||||
| JP2004185659A | ||||
| JP2005116102A |
Attorney, Agent or Firm:
Longhua International Patent Service Corporation