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Title:
FLAT GAIN AMPLIFIER
Document Type and Number:
Japanese Patent JPH04292006
Kind Code:
A
Abstract:

PURPOSE: To make a bias circuit unnecessary, and also, to widen a flat gain band in respect of a flat gain amplifier by a CMOS circuit.

CONSTITUTION: First p- and n-channel field effect transistors 3,4 are cascade- connected between power supply 1 and the ground 2, and the gates of these transistors 3,4 are connected in common so as to be an input terminal 5. Besides, second p- and n-channel field effect transistors 6,7 are cascade-connected between the power supply 1 and the ground 2, and their cascade-connection point, the gates of these transistors 6,7, and the cascade-connection point of the first p- and n-channel field effect transistors 3,4 are connected in common so as to be an output terminal 8.


Inventors:
UENO NORIO
MATSUYAMA SATORU
Application Number:
JP8041891A
Publication Date:
October 16, 1992
Filing Date:
March 20, 1991
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03F1/42; H03F3/18; H03F3/30; (IPC1-7): H03F1/42; H03F3/18; H03F3/30
Attorney, Agent or Firm:
Shoji Kashiwaya (1 person outside)