Title:
FLAT PANEL SENSOR
Document Type and Number:
Japanese Patent JP3697827
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a high-performance flat panel sensor from which signal readout noise and the delay, etc., of gate signals supplied to pixel TFT elements are reduced.
SOLUTION: The number of pixel rows (or columns) allotted to one data line is reduced so as to reduce the data line capacity of each data line, by dividing data lines arranged at every pixel row (or column) into two Sa1,..., Sa7 and Sb1,..., Sb7) on a panel 1, and arranging charge sensitive amplifiers As1,..., As7 and Ab1,..., Ab7 on both sides of the panel 1 correspondingly to the data lines. In addition, the distances from gate control circuits to TFT elements are shortened so as to reduce the delays of gate signals, by dividing gate lines arranged at every pixel row or column into two on the panel 1, and arranging the gate control circuits on both sides of the panel 1 corresponding to the gate lines.
Inventors:
Oikawa Shiro
Application Number:
JP8046897A
Publication Date:
September 21, 2005
Filing Date:
March 31, 1997
Export Citation:
Assignee:
SHIMADZU CORPORATION
International Classes:
G01T1/24; H01L27/14; H01L27/146; H01L29/786; H04N5/32; H04N5/335; H04N5/341; H04N5/357; H04N5/369; H04N5/374; (IPC1-7): H01L27/14; H01L27/146; H04N5/32; H04N5/335
Domestic Patent References:
| JP9219823A | ||||
| JP2253186A | ||||
| JP4004663A | ||||
| JP7235652A |
Attorney, Agent or Firm:
Yoshiro Kurauchi