Title:
平坦化ＶＣＳＥＬおよびその作製方法
Document Type and Number:
Japanese Patent JP7050124
Kind Code:
B2
Abstract:
An etched planarized VCSEL includes: an active region; a blocking region over the active region, and defining apertures therein; and conductive channel cores in the apertures, wherein the conductive channel cores and blocking region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the blocking region over the active region; etching the apertures in the blocking region; and forming the conductive channel cores in the apertures of the blocking region. Another etched planarized VCSEL includes: an active region; a conductive region over the active region, and defining apertures therein; and blocking cores in the apertures, wherein the blocking cores and conductive region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the conductive region over the active region; etching the apertures in the conductive region; and forming the blocking cores in the apertures of the conductive region.
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Inventors:
Graham, Luke
Mackines, Andy
Mackines, Andy
Application Number:
JP2020125100A
Publication Date:
April 07, 2022
Filing Date:
July 22, 2020
Export Citation:
Assignee:
Finisar Corporation
International Classes:
H01S5/183; H01S5/323
Domestic Patent References:
| JP6069585A | ||||
| JP11121864A | ||||
| JP2006261316A |
Foreign References:
| US20050025206 |
Attorney, Agent or Firm:
Makoto Onda
Hironobu Onda
Atsushi Honda
Hironobu Onda
Atsushi Honda
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