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Title:
FLIP-FLOP CAPABLE OF COUNTING AND INITIAL SETTING
Document Type and Number:
Japanese Patent JPS55124330
Kind Code:
A
Abstract:

PURPOSE: To simplify the circuit constitution as well as realize both the miniaturization and the low power consumption, by forming the additional circuit of the initial value setting function with the FF circuit and the logic gate which is capable of the high-speed action for the initial value setting.

CONSTITUTION: Initial setting input terminal 15 and counting-initial setting switch terminal 11 are connected to the input ends of the 1st and the 2nd NAND gates 31 and 32. And the output of gates 31 and 32 are supplied to the 3rd NAND gate 33. Furthermore, the output of gate 31 is supplied to the 4th NAND gate 34, and the output of gates 32 and 34 are supplied to NAND gate 35. The output of gate 33 is applied to reset terminal R of FF circuit 18; the output of gate 35 is applied to set terminal S of circuit 18; and the clock pulse sent from clock terminal 21 is applied to trigger terminal T. Then the number of the gates is reduced for the range during which signal R applied to terminal 11 reaches reset terminal R, and thus the speed of the initial value setting action is increased. And the counting speed is decided according to the velocity performance of circuit 18. In this way, the circuit constitution can be simplified.


Inventors:
AKAZAWA YUKIO
SUDOU TSUNETAKA
MURATA MASANORI
ITOU MITSUTOSHI
Application Number:
JP3193379A
Publication Date:
September 25, 1980
Filing Date:
March 19, 1979
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
NIPPON ELECTRIC CO
International Classes:
H03K21/38; H03K3/037; H03K23/00; (IPC1-7): H03K21/32



 
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