To relax a trade-off relation between a high-speed operation and a wide operating frequency range of an apparatus, in a frequency divider utilizing a current logic type flip-flop circuit.
A latch pair part L is divided into a first latch pair part L1 and a second latch pair part L2. For the second latch pair part L2, an operational current controller CC is provided. The operational current controller CC performs control to increase an operational current to the second latch pair part L2 as the frequency of a clock CLK becomes low. When a third switch SW3 is OFF, an operational current balance controller BC reduces an operational current to the first latch pair part L1 or to a sample pair part S so as to cancel a component varied by the current control, so that an output amplitude of data is made constant.
COPYRIGHT: (C)2010,JPO&INPIT
| JP6291618A | ||||
| JP200022502A | ||||
| JP2006115234A |
Takashi Nishikawa
Funabashi Kuninori