Title:
FLIP-FLOP CIRCUIT AND SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3692032
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce power being consumed in a clock tree without increasing the layout area and internal power consumption.
SOLUTION: A clock generating circuit generates a first clock signal and a second clock signal delayed behind the first clock signal. A switch circuit for transmitting an inputted logical value to the output, during an interval where the first clock signal has a high level and the second clock signal has a low level and during an interval where the first clock signal has a low level and the second clock signal has a high level, is disposed at the prestage of a logical value holding circuit in the flip-flop circuit. According to the arrangement, power consumption can be reduced without increasing the layout area.
Inventors:
Fujio Ishihara
Application Number:
JP2000402735A
Publication Date:
September 07, 2005
Filing Date:
December 28, 2000
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H03K5/151; H03K3/037; (IPC1-7): H03K3/037; H03K5/151
Domestic Patent References:
| JP6152336A | ||||
| JP946185A | ||||
| JP62262511A |
Attorney, Agent or Firm:
Hidekazu Miyoshi
Iwa Saki Kokuni
Kawamata Sumio
Nakamura Tomoyuki
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu
Iwa Saki Kokuni
Kawamata Sumio
Nakamura Tomoyuki
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu
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