Title:
FLIP-FLOP CIRCUIT
Document Type and Number:
Japanese Patent JP2933022
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent data-through by decreasing a size of a master transistor(TR) more than a slave TR for decreasing a latch time of a master side latch hold circuit, thereby forming an interval in latch states of the both.
SOLUTION: A size of transistors(TRs) 8, 16 is selected smaller to be 80% of a size of TRs 7, 15, 19, 20. Thus, a collector current of the TRs 8, 16 is only 80% of a collector current of the TRs 7, 15. Thus, a gradient of leasing and trailing of a collector current of the current source TR 8, relating to the master side latch is slower than that of the TR 7. Thus, the time in the latch state of the master side latch hold circuit is decreased, and the time in the hold state is extended. Similarly, the latch time of the slave side latch hold circuit is decreased, and the time of the hold state is extended. Thus, the interval between latch states of the master side and the slave side is provided, and data-through of the both is prevented.
Inventors:
UEMURA MICHIHIKO
Application Number:
JP22037196A
Publication Date:
August 09, 1999
Filing Date:
August 02, 1996
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H03K19/086; H03K3/286; H03K3/289; (IPC1-7): H03K3/289; H03K3/286; H03K19/086
Attorney, Agent or Firm:
Asato Kato
Previous Patent: COMMUNICATION NETWORK FAILURE RESTORATION SYSTEM
Next Patent: SCENERY IMAGE INPUT AND TOUCH OUTPUT DEVICE
Next Patent: SCENERY IMAGE INPUT AND TOUCH OUTPUT DEVICE