PURPOSE: To facilitate the design of a scan path circuit by providing a first latch circuit for latching and outputting input data by a clock signal, and latching and outputting output data of this first latch circuit by the clock signal being as it is which can switch is selectively or the delayed clock signal.

CONSTITUTION: In the case of the mode in which a selector 4 inputs a clock signal CK to a latch circuit 2 without allowing it to a pass through a delaying circuit 3 by a selection control signal SC, a general operation (a) of a flip-flop circuit is executed, and in the case of the mode in which the selector 4 inputs the clock signal CK to the latch circuit 2 through the delaying circuit 3 by the selection control signal SC, an operation (b) is executed. In the case of this operation (b), the timing for holding and outputting the data is delayed by a delay time (d) of the delaying circuit 3 from the clock signal CK. In such a way, a scan path circuit can be designed easily.