PURPOSE: To improve the reliability of a combinational logical circuit to be tested by enabling the inspection of a set/reset signal at the time of performing a scan pass test.

CONSTITUTION: At the time of performing a scan pass test, multiplexers M11 and M12 supply a set signal I16 to be supplied from a combinational circuit L1 to data terminals D1, D2 of primitive flip-flop circuits PF11, PF12 in response to control signals I14, I15, I24 and I25, and enables the signal to be read as data. Thus, as the abnormality of the set signal caused by the fault of the combinational logical circuit can be detected, the fault detection rate of a combinational logical circuit can be improved.