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Title:
FLIP-FLOP CIRCUIT
Document Type and Number:
Japanese Patent JPH0537306
Kind Code:
A
Abstract:

PURPOSE: To prevent an output from becoming indefinite, even if a signal is inputted simultaneously to a set input terminal and a reset input terminal of a flip-flop by simplifying the circuit configuration.

CONSTITUTION: In input parts of an S terminal and an R terminal of an SR type flip-flop, D-type flip-flops 4 and 4 for detecting a rise edge of an input pulse and outputting an impulse-like pulse are constituted. In such a way, since set and reset of the flip-flop 5 are operated by an edge trigger, even if a state that the S terminal and the R terminal become an 'H' input simultaneously exists, it does not occur that an output becomes indefinite.


Inventors:
MASAYANAGI HIROYUKI
HIRAGA MASATOMI
Application Number:
JP21139691A
Publication Date:
February 12, 1993
Filing Date:
July 30, 1991
Export Citation:
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Assignee:
NEC CORP
MIYAGI NIPPON DENKI KK
International Classes:
H03K3/037; H03K3/286; (IPC1-7): H03K3/037; H03K3/286
Attorney, Agent or Firm:
Masaki Yamakawa



 
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