To attain a stable operation at all times by operating 1st and 2nd pMOS transfer gates receiving a clock input signal and 3rd and 4th nMOS transfer gates receiving a data input signal independently of each other.

When a clock input signal CK descends from 'H' to 'L', 1st and 2nd pMOS transfer gates 54, 55 are conductive, 3rd nMOS transfer gate 56 is conductive and 4th nMOS transfer gate 57 is nonconductive. On the other hand, when the signal CK rises from 'L' to 'H', 5th and 6th nMOS transfer gates 61, 62 are conductive and 7th, 8th nMOS transfer gates 63, 64 are nonconductive. The clock input signal transfer gates 54, 55 and data signal transfer gates 56, 57 are operated independently of each other, then there is no limit in the timing between the clock input signal and the data input signal D and the operation stable at all times is operated.